Technology

AMD Files A Patent For Scalable GPUs Based On Chips

At AMD, based on practical experience with CPUs, they are completely convinced of the modular chiplet architecture. In the future, the company also wants to use this design for GPUs – and had to solve some additional problems for this.

AMD successfully relies on the multi-chip module (MCM) design for various current CPUs. Several fully-fledged processors are connected to one another. Compared to the previously used multi-core architectures in a monolithic design, this allows significantly more flexible scaling, which reduces development and production costs, especially for chips that are only manufactured in smaller numbers.

However, it has so far proven difficult to apply the method to graphics processors as well, as these are significantly more complex than normal CPUs from the start. But now AMD has patented a method with which the previous problems can possibly be solved. That comes from a report by WCCFTechh.

Multi-GPU model

The previous attempts with MCM designs in the GPU area have shown that the latencies between the chips were far too high. In addition, there were difficulties with the programming models, as the parallel distribution of tasks was much more difficult to handle. AMD now wants to solve these problems with passive crosslinks between the individual chipsets and the other system components.

Every GPU chiplet should be able to communicate directly with the CPU. It also gets its own cache. Basically, the design boils down to the fact that the graphics card does not appear to the outside as a system with a GPU, but rather a computer architecture with several graphics chips that can be controlled independently of each other.

In this way, the problem of latency-afflicted communication between the chiplets is prevented. The developer no longer has to worry about how the load is distributed on the GPU. There are now sufficient software solutions from the HPC segment, in which many graphics units have been used for a long time, for distributing the tasks to many graphics processors.

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