Samsung is now nailing its heads in its foundry roadmap: From 2025, the company wants to be able to manufacture chips on a large scale that are manufactured with a structure size of 2 nanometers.
Samsung will then work with Gate-All-Around (ATM) technology in this area. This replaces the fin-shaped field-effect transistors (FinFETs) that are common today, as these quickly lose their performance advantages in ever smaller structures. Even at 3 nanometers, Samsung will rely on GAA, which the developers of the group presented to the public for the first time in 2019.
In the industry, the process is practically the standard for the coming chip generations. IBM and TSMC have also announced that they want to work with this technology. The name is derived from the fact that the transistor channels run through the gate fin and are thus surrounded by its material, which significantly reduces the space requirement.
Big investments required
Samsung uses the ATM process in the Multi-Bridge-Channel FET (MBCFET) processes, with which the first generation of 3-nanometer chips are to be manufactured. According to the company, these offer several advantages compared to the 5-nanometer process: The result will be 35 percent smaller chips with the same number of transistors, which work with 30 percent higher performance and 50 percent lower energy consumption.
In the meantime, the roadmap had to be adjusted a bit with regard to the 3-nanometer process. Samsung will not be able to come up with the first batches this year. Instead, they want to be ready in the first half of 2022. An improved version should also be launched in the following year.
In the course of this, Samsung reaffirmed that considerable investments will be made in the production facilities. The aim is to significantly expand the foundry capacities and, above all, hopes to win numerous customers who prefer not to have production in China in order to avoid geopolitical problems.
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