At the forefront of chip manufacturing processes, things are really moving to the fringe of what can still be physically represented with conventional processes: TSMC is on track with 3 nanometers and has a 2-nanometer deadline. According to the company, the production processes for architectures with a structure width of 3 nanometers should be able to start at least this year.
Compared to the previous 5-nanometer design, a 15 percent increase in performance is achieved with the same power consumption or the same performance with 30 percent less power consumption. it was said that With this technology, the contract manufacturer is setting the pace in the industry so clearly that not only the previously important customers want to rely directly on the new process. There are also competitors who want to play at the top themselves, but can’t keep up with TSMC.
This is specifically about Intel. The group is still lagging behind in the further development of its production processes and therefore wants to have the chiplets, from which the future Xeon processors and also new GPUs are manufactured, manufactured by TSMC in a 3-nanometer version.
2nm is coming in 2025
In addition, TSMC is already working on the imminent introduction of 2-nanometer technology. “Our N2 development is on track,” said CC Wei, CEO of TSMC. This process technology should then be available from 2025. A year earlier, the process was extensively tested during the production of smaller series.
However, the technology is not yet sufficiently developed to produce enough chips in a short time for mass-produced products such as Apple’s iPhone. But the chip industry also has to look for new processes. A further reduction in the size of the structures is hardly possible with the materials and production techniques used so far. However, there are promising approaches, at least in the areas of research, which, however, will also lead to major changes in the industry.
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